RISC-V - Revision history

Popolon: /* Introduction */ add link to RISC-V Code Size Reduction Group and explain what means ISA here

2024-04-18T21:10:42Z

‎Introduction: add link to RISC-V Code Size Reduction Group and explain what means ISA here

Popolon: /* Registers */ space between general definition and compressed format

2024-02-08T20:46:21Z

‎Registers: space between general definition and compressed format

Popolon: /* Registers */

2024-02-08T20:45:34Z

‎Registers

Popolon: /* Registers */

2024-02-08T20:45:16Z

‎Registers

Popolon: /* General options and 16bits Compressed mnemonics extension */ readelf -S shows more segments than objdump -x

2024-02-04T17:47:46Z

‎General options and 16bits Compressed mnemonics extension: readelf -S shows more segments than objdump -x

Popolon: /* Testing it */ +execute risc-v binary transparently on non-RISC−V systems

2024-02-02T21:08:53Z

‎Testing it: +execute risc-v binary transparently on non-RISC−V systems

Popolon: /* Assembler, compiler, linker */ send to bottom chapter to various method of runing risc-v code

2024-02-02T20:59:44Z

‎Assembler, compiler, linker: send to bottom chapter to various method of runing risc-v code

Popolon: /* Assembler, compiler, linker */ more information about available tools

2024-02-02T20:58:15Z

‎Assembler, compiler, linker: more information about available tools

Popolon: /* General options and 16bits Compressed mnemonics extension */ example of li

2024-02-02T20:21:21Z

‎General options and 16bits Compressed mnemonics extension: example of li

Popolon: /* Nomenclature and extensions */

2024-02-02T20:19:51Z

‎Nomenclature and extensions

@@ Line 1: / Line 1: @@
 == Introduction ==
-RISC-V is an open and free standard or RISC ISA. It exists in 32,64 and still in draft stage, 128 bits wide versions. There are lot of free or non free implementations. You can find software, FPGA, or ASIC implementations on most codeforges like Github, Gitlab, Gitea, etc... Several research institute around the world also opened their own versions.
+RISC-V is an open and free standard or RISC ISA (Instruction Set Architecture). It exists in 32,64 and still in draft stage, 128 bits wide versions. There are lot of free or non free implementations. You can find software, FPGA, or ASIC implementations on most codeforges like Github, Gitlab, Gitea, etc... Several research institute around the world also opened their own versions.
 === The RISC-V processor ISA  ===

@@ Line 71: / Line 71: @@
 === Registers ===
-Registers in assembly language can be called x0-x31 or by their specific functions. x0 is always 0 and can't be changed. In compressed mnemonics, only 8 registers are available, due to 3bits limit of the register field in this case. Theses registers are for integer, x8-x15 or s0,s1,a0-a5 (in ABI), and for floats f8-f15 or in ABI fs0,fs1,fa0-fa5. An assembler error will occur if you try to use other registers with c. mnemonics, or a pseudo-instruction will be translated in non c. mnemonic.
+Registers in assembly language can be called x0-x31 or by their specific functions. x0 is always 0 and can't be changed.
 == Tools ==

@@ Line 71: / Line 71: @@
 === Registers ===
-Registers in assembly language can be called x0-x31 or by their specific functions. x0 is always 0 and can't be changed. In compressed mnemonics, only 8 registers are available, due to 3bits limit of the register field in this case. Theses registers are for integer, x8-x15 or s0,s1,a0-a5 (in ABI), and for floating f8-f15 or in ABI fs0,fs1,fa0-fa5. An assembler error will occur if you try to use other registers with c. mnemonics, or a pseudo-instruction will be translated in non c. mnemonic.
+Registers in assembly language can be called x0-x31 or by their specific functions. x0 is always 0 and can't be changed. In compressed mnemonics, only 8 registers are available, due to 3bits limit of the register field in this case. Theses registers are for integer, x8-x15 or s0,s1,a0-a5 (in ABI), and for floats f8-f15 or in ABI fs0,fs1,fa0-fa5. An assembler error will occur if you try to use other registers with c. mnemonics, or a pseudo-instruction will be translated in non c. mnemonic.
 == Tools ==

@@ Line 71: / Line 71: @@
 === Registers ===
-Registers in assembly language can be called x0-x31 or by their specific functions. x0 is always 0 and can't be changed.
+Registers in assembly language can be called x0-x31 or by their specific functions. x0 is always 0 and can't be changed. In compressed mnemonics, only 8 registers are available, due to 3bits limit of the register field in this case. Theses registers are for integer, x8-x15 or s0,s1,a0-a5 (in ABI), and for floating f8-f15 or in ABI fs0,fs1,fa0-fa5. An assembler error will occur if you try to use other registers with c. mnemonics, or a pseudo-instruction will be translated in non c. mnemonic.
 == Tools ==

@@ Line 67: / Line 67: @@
   riscv64-elf-objdump -d -M no-aliases tinydemo
-The option -x of objdump allow to see all the segments of the ELF binary. There is probably still some byte to gain there :):
+The option <code>-x</code> of <code>objdump</code> allow to see all the most segments of the ELF binary, but due to its usage to libBDF decoding, it only contains some part. The <code>readelf</code> tool (also part of GNU binutils) display all real segments with <code>-S</code> option. There is probably still some byte to gain there :).
-  riscv64-elf-objdump -x tinydemo
+  riscv64-elf-readelf -S tinydemo
 === Registers ===

@@ Line 89: / Line 89: @@
 === Testing it ===
 If you don't have one of those cheap boards, you can still test RISC-V assembly on an emulator.
 Qemu allow to execute RISC-V application or systems on any kind of architectures. You can use the same tricks than used on x86 to reduce the binary size of the ELF binary format made with GNU tools.
 The main author of Qemu also made [https://bellard.org/tinyemu/ TinyEmu], a RISC-V only tiny emulator, it already has WASM ports, so you can play with it on the web.

@@ Line 83: / Line 83: @@
 * Arduino has several RISC-V implementations.
-* It exists various assembler, simulators, emulators (Qemu, TinyEMU, RVVM,… including WASM versions), various FPGA softcore implementations of RISC-V, and finally lot of cheap ASIC/boards hardware ones.
+* It exists various assembler, simulators, emulators (Qemu, TinyEMU, RVVM,… including WASM versions), various FPGA softcore implementations of RISC-V, and finally lot of cheap ASIC/boards hardware ones see below for various methods for running RISC-V code.
 Most other languages are also available in RISC-V instruction set. Some Linux distribution have been ported and ISO are available (Debian, Ubuntu for example). Haiku OS also work on RISC-V platform, and there are plenty of embedded OS working on it (Arduino, FreeRTOS, HarmonyOS, LiteOS, RT-Thread, RustOS, Zephyr...).

@@ Line 75: / Line 75: @@
 == Tools ==
 ==== Assembler, compiler, linker ====
-* GNU tools contains both RISC-V 32 and 64bits compiler (GCC), assembler,linker,striper (gnu-binutils) and debugger (GDB), they are available for native or cross-compiling on most GNU/Linux distribution.
+* GNU tools  contains both RISC-V 32 and 64bits compiler (in [https://gcc.gnu.org/ GCC]), assembler (as), linker (ld), striper (strip), dumper/disassembler (objdump) contained in ([https://www.gnu.org/software/binutils/ gnu-binutils]) and debugger ([https://www.sourceware.org/gdb/ GDB], GNU Debugger), they are available for native or cross-compiling on most GNU/Linux distribution.
 * [https://github.com/theandrew168/bronzebeard Bronzebeard] is a standalone assembler for developing bare metal RISC-V programs. It has been used mainly on Longan Nano a RV32 board generally sold with an LCD screen. There are few demo on this board. The initialisation of the screen on this platform has an important footprint that can't allow to go in 128B or 256B competitions.
 * Arduino has several RISC-V implementations.
 Most other languages are also available in RISC-V instruction set. Some Linux distribution have been ported and ISO are available (Debian, Ubuntu for example). Haiku OS also work on RISC-V platform, and there are plenty of embedded OS working on it (Arduino, FreeRTOS, HarmonyOS, LiteOS, RT-Thread, RustOS, Zephyr...).

@@ Line 43: / Line 43: @@
 OS like Debian use RV64GC as default compiler extensions options. This mean General (IMAF) + Compressed instructions. Compressed mnemonics (assembly instructions) are a limited subset of mnemonics, that all fits on 16 bits. They are prefixed by <code>c.</code>, and described in "Chapter 16 . “C” Standard Extension for Compressed Instructions, Version 2.0", page 97, of  of the current specifications : "[https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf The RISC-V Instruction Set Manual - Volume I: Unprivileged ISA - Document Version 20191213]".
-RISC-V Assembly language use pseudo-instructions, and assemblers like those of GCC or CLANG, convert them with their best efforts to more optimised ones, using compressed version, if the C flag is passed to --march argument:
+RISC-V Assembly language use pseudo mnemonics (<code>li</code>=load immediate, is one of them) and assemblers like those of GCC or CLANG, convert them with their best efforts to more optimised ones, using compressed version, if the C flag is passed to --march argument:
 if f(loat) option is passed (as in imafc or gc), the final executable is a bit bigger than without it. So it can be interesting to limit extensions to really used one. However it can be useful to have access to floats numbers in demos.

← Older revision		Revision as of 20:19, 2 February 2024
Line 39:		Line 39:

	* Crypto extension is frozen, and should be available in October.		* Crypto extension is frozen, and should be available in October.
		+
		+	==== General options and 16bits Compressed mnemonics extension ====
		+	OS like Debian use RV64GC as default compiler extensions options. This mean General (IMAF) + Compressed instructions. Compressed mnemonics (assembly instructions) are a limited subset of mnemonics, that all fits on 16 bits. They are prefixed by <code>c.</code>, and described in "Chapter 16 . “C” Standard Extension for Compressed Instructions, Version 2.0", page 97, of of the current specifications : "[https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf The RISC-V Instruction Set Manual - Volume I: Unprivileged ISA - Document Version 20191213]".
		+
		+	RISC-V Assembly language use pseudo-instructions, and assemblers like those of GCC or CLANG, convert them with their best efforts to more optimised ones, using compressed version, if the C flag is passed to --march argument:
		+
		+	if f(loat) option is passed (as in imafc or gc), the final executable is a bit bigger than without it. So it can be interesting to limit extensions to really used one. However it can be useful to have access to floats numbers in demos.
		+
		+	An example of building script with stripping if floats aren't used. You can decide to pass (tinydemo.s) or not the .s (tinydemo) to the script:
		+	<pre>
		+	file=${1//.s}
		+	riscv64-elf-as -march=rv64imac -o $file.o $file.s
		+	riscv64-elf-ld -o $file $file.o
		+	riscv64-elf-strip --strip-all $file
		+	</pre>
		+
		+	A similar script with clang. <code>-s</code> shorter version of <code>-strip-all</code> can be used. It make slightly bigger elf executables.
		+	<pre>
		+	file=${1//.s}
		+	clang --target=riscv64 -march=rv64imac -mno-relax ${file}.s -c -o ${file}.o
		+	ld.lld -strip-all ${file}.o -o ${file}
		+	</pre>
		+
		+	To disassemble the executable file, you can use gnu objdump with -d option:
		+	riscv64-elf-objdump -d tinydemo
		+	However. This show pseudocode version of the software. To display mnemonics really used, add the option <code>-M no-aliases</code> as is:
		+	riscv64-elf-objdump -d -M no-aliases tinydemo
		+
		+	The option -x of objdump allow to see all the segments of the ELF binary. There is probably still some byte to gain there :):
		+	riscv64-elf-objdump -x tinydemo

	=== Registers ===		=== Registers ===