Difference between revisions of "RISC-V CPUs"

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== Introduction ==
 
== Introduction ==
RISC-V is an open and free standard or RISC ISA. It exists in 32,64 and 128 (still in draft stage) bits wide versions. There are lot of free or non free implementations. You can find software, FPGA, or ASIC implementations on most codeforges like Github, Gitlab, Gitea, etc... Several research institute around the world also opened their own versions.
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RISC-V is an open and free standard or RISC ISA. It exists in 32,64 and still in draft stage, 128 bits wide versions. There are lot of free or non free implementations. You can find software, FPGA, or ASIC implementations on most codeforges like Github, Gitlab, Gitea, etc... Several research institute around the world also opened their own versions.
  
 
=== The RISC-V processor ISA  ===
 
=== The RISC-V processor ISA  ===

Revision as of 13:21, 29 September 2021

Introduction

RISC-V is an open and free standard or RISC ISA. It exists in 32,64 and still in draft stage, 128 bits wide versions. There are lot of free or non free implementations. You can find software, FPGA, or ASIC implementations on most codeforges like Github, Gitlab, Gitea, etc... Several research institute around the world also opened their own versions.

The RISC-V processor ISA

The RISC-V Processor is a RISC based architecture, with less instructions than most other RISC processors. For example, there is no GT (>) or GE (>=) hardware instructions, only LT (<) or LE (<=) instruction, but the RISC-V assembly language support GT and GE, and switch it to LT/LE by switching also registers to keep the test as needed.

One of the main goals of the specifications is to have modularity with high granularity. So bitwise operators, multiplications/divisions, vector instructions for example are on different optional extensions, that can be implemented or not by RISC-V processor makers, reducing the total number of transistors depending on processor usage. Each extension have its own letter added in the name of the processor.